Efforts have been made to enhance performance of an IGBT by carrying out many improvements. Here, the performance of an IGBT is identified as a switch that completely cuts off current while holding an applied voltage when turned-off, and allows current to flow with the least possible voltage drop, i.e., with the least possible on-resistance. For purposes of an operation an IGBT, a collector is typically expressed as an “anode” and an emitter is typically expressed as a “cathode.”
There exists a tradeoff relationship between the maximum voltage that can be held by an IGBT, i.e., a magnitude of a breakdown voltage, and a voltage drop when the IGBT is turned-on, where an IGBT with a higher breakdown voltage has a higher on-voltage. Ultimately, the limit of the optimum value in the tradeoff relation is determined by physical properties of silicon. For enhancing the optimum value in the tradeoff, property/structural changes are needed to prevent a local electric field concentration buildup when an IGBT holds an applied voltage.
Another important measure representing performance of an IGBT is a tradeoff between an on-voltage and a switching loss (in particular, a turn-off loss). An IGBT, being a switching device, carries out an operation from being turned-on to being turned-off, or from being turned-off to being turned-on. At an instant of such a switching operation, a large loss is produced per unit time. In general, an IGBT with a lower on-voltage is turned-off more slowly and produces a larger turn-off loss. By improving such a tradeoff, performance of an IGBT can be enhanced. Note that a turn-on loss of an IGBT has a little dependence on the on-voltage, but rather largely depends on the characteristics of the free-wheeling diode used in combination with the IGBT.
For optimizing the tradeoff between the on-voltage and the turn-off loss (hereinafter referred to as an on-voltage to turn-off loss relation), it is effective to optimize a distribution of excessive carriers in an IGBT in a turned-on state. For lowering the on-voltage, the amount of excessive carriers can be increased to lower the resistance value of a drift layer. At the turning-off state, however, all of the excessive carriers must be swept out from the device or made to disappear by an electron-hole recombination. Thus, increasing the amount of excessive carriers increases the turn-off loss. Therefore, for optimizing such a tradeoff, it is necessary to minimize the distribution of excessive carriers that causes the turn-off loss by the same lowered on-voltage.
For achieve the optimum tradeoff, it is necessary to lower the carrier concentration on the anode side while increasing the carrier concentration on the cathode side to thereby provide a ratio of the carrier concentration on the anode side to the carrier concentration on the cathode side to about 1:5. Furthermore, it is also necessary to hold the carrier lifetime in the drift layer longest possible so that an averaged carrier concentration in the drift layer becomes high.
When an IGBT is turned-off, the depletion layer expands from the p-n junction on the cathode side to the inside of the drift layer with progress toward the anode layer on the bottom surface. At this time, of excessive carriers in the drift layer, holes are drawn out by an electric field from the end of the depletion layer. This creates an electron excessive state, where the excess electrons are injected into the anode layer in a p-type through a neutral region. Thus, the p-n junction on the anode side is slightly forward-biased, which causes reverse injection of holes with the amount depending on the amount of the injected electrons. The holes brought by the reverse injection merge with holes drawn out by the above-explained electric field and enter the depletion layer.
Carriers (here, holes) carrying electric charges pass through the region of the electric field toward the cathode side. Thus, work is to be done in the electric field on the carriers. The work done on the carriers in the electric field eventually causes lattice vibration of crystal lattices, such as those of silicon, due to collisions of carriers with the crystal lattices, and is dissipated as heat. The dissipated energy becomes the turn-off loss. Note that the energy dissipated due to the carriers drawn out before the depletion layer has extended out is smaller than the energy dissipated due to the carriers being drawn out when the depletion layer has extended out. This is because the depletion layer before having extended out provides a small potential difference when the carriers pass through the depletion layer, by which small work is done in the depletion layer on the carriers in the electric field.
The above explanation is made from the microscopic viewpoint. From the macroscopic view point of the terminal voltage of a device, it means that current flowing before the anode-cathode voltage has finished rising, i.e., flowing while the anode-cathode voltage is rising, makes a smaller contribution to the loss expressed by the product of the voltage and the current (voltage×current) than the current flowing after the anode-cathode voltage has finished rising. From the foregoing, it is known that a carrier distribution deviating to the cathode side by the later-described IE effect causes a smaller turn-off loss than the carrier distribution deviating to the anode side under conditions that a fraction of carriers drawn out under a low voltage is larger and on-voltages to both the distributions are the same.
The carrier concentration on the anode side can be reduced by reducing the total amounts of impurity concentrations in the anode layer. This is not so difficult in itself. However, in an IGBT with a low rated breakdown voltage, such as 600V, for reducing the total amounts of impurity concentrations in the anode layer, the thickness of the wafer must be brought to on the order of 100 μm or below. Because such a thin wafer must be handled during the manufacturing process, the manufacturing technique becomes complicated and difficult. Also, the carrier concentration on the cathode side is increased due to the IE effect.
For a cathode structure with a large IE effect, a structure such as the HiGT structure is proposed in which an n-layer with a high impurity concentration is inserted in a cathode so as to surround a p-base of a planar structure (see JP-A-2003-347549 and JP-T-2002-532885, for example). Moreover, in a trench gate structure, structures such as a CSTBT structure, in which an n-layer having a higher impurity concentration than a drift layer is inserted in a mesa section between the adjacent trenches, and an IEGT (Injection Enhancement Gate Transistor) structure (see JP-A-8-316479, and Omura, et al, “Carrier injection enhancement effect of high voltage MOS devices-Device physics and design concept-”, ISPSD '97, pp. 217-220, for example), have been proposed. In general, the IE effect in the trench structure is larger than that in the planar structure.
The IE effect is discussed and reported in Udrea, et al, “A unified analytical model for the carrier dynamics in Trench Insulated Gate Bipolar Transistor (TIGBT),” ISPSD '95, pp. 190-195, for example. An often drawn equivalent circuit of an IGBT is a combination of a MOSFET (Insulated Gate Field Effect Transistor having a Metal-Oxide-Semiconductor structure) and a bipolar transistor. However, with an actual device operation taken into consideration, the equivalent circuit can be regarded, as an equivalent circuit shown in present FIG. 1, which is a combination of a MOSFET 1, a p-n-p bipolar transistor 2, and a p-i-n diode 3 (also disclosed in a co-pending application filed concurrently herewith).
FIG. 2 schematically illustrates a cross sectional view showing an arrangement of a principal part of a planar IGBT. In FIG. 2, the right region 4 identified in dashed lines denotes a p-n-p bipolar transistor region (hereinafter referred to as a p-n-p BJT region) and the left region 5 identified in dashed lines denotes a p-i-n diode region. Moreover, in FIG. 2, the arrows in solid lines represent flow of electron current, while the arrows in dotted lines represent flow of hole current. In the present disclosure, the leading character “n” or “p” preceding the names of the layers and regions means that the majority carriers in the layers and the regions are electrons or holes, respectively. Moreover, a region (including a layer) named with a leading character “n+” or “p+” means that the region (including the layer) has a higher impurity concentration than the region (including the layer) named with the leading character “n” or “p” without the sign “+”, respectively. Furthermore, a region (including a layer) named with a leading character “n++” means that the region (including the layer) has a higher impurity concentration than the region (including the layer) named with the leading character “n+”.
As shown in FIG. 2, electrons flow from an n++-region 6 on the surface of a MOS section to a p-anode layer 11 on the bottom surface through an n+-inversion layer 8 on a p-layer 7 surrounding the n++-region 6 and an n+-electron accumulation layer 10 on the surface of an n−-drift layer 9. Part of the electron current becomes a base current of the p-n-p BJT region 4. In the p-n-p BJT region 4, holes flowing from the p-anode layer 11 by diffusion or drift are only flow in the p-layer 7, and the p-n junction between the p-layer 7 and the n−-drift layer 9 is slightly reverse-biased. Therefore, the concentration of minority carriers, i.e., holes in the n−-drift layer 9 near the p-n junction is extremely low.
The n-cathode in the p-i-n diode region 5 is the n+-electron accumulation layer 10 on the surface of the n−-drift layer 9. Since the junction between the n+-electron accumulation layer 10 and the n−-drift layer 9 (hereinafter abbreviated as the n+/n−-junction) is slightly forward-biased, electrons are injected into the n−-drift layer 9. When large current flows, an electron concentration becomes far higher than the doping concentration in the n−-drift layer 9 (a high-injection state). Moreover, for satisfying the charge neutrality condition, there exist holes with the same concentration as that of electrons. Therefore, the concentration of minority carriers, i.e., holes, in the n-drift layer 9 near the n+/n−-junction is extremely high.
For achieving the optimum carrier distribution with a deviation to the cathode side in an IGBT, it is important to reduce the p-n-p BJT region 54 and to increase a p-i-n diode region 55. Moreover, it is very important to increase the amount of forward bias across the n+/n− junction to enhance electron injection. In every previously proposed structure having the IE effect, proportion of the p-i-n diode region is increased while attaining an increase in an amount of forward bias across the n+/n−-junction.
Note that in an IGBT with a planar structure, reduction in proportion of a region occupied by a p-base in a cell pitch reduces an on-voltage. The reason for this is due to the increase in the proportion of the p-i-n diode region with an additional rise in a lateral current density near the surface that caused an increase in a voltage drop, which enhances the effect of increasing the forward bias across the n+/n− junction. The reason for increasing the forward bias across the n+/n−-junction is that the electric potential of the n+-layer, having low resistance, is equal to the cathode electric potential, while the electric potential of the n−-layer, having high resistance, is raised by the voltage drop due to the large current.
In the same way, in an IGBT with a trench structure, by reducing proportion of the p-n-p BJT region, the IE effect can be enhanced. Reduction in proportion of the p-n-p BJT region can be made by bringing the p-base region to a floating state in a mesa section, for example. Moreover, the IE effect can be also enhanced by making the trench deeper to isolate the bottom of the trench from the p-n junction. Furthermore, by narrowing the width of the mesa section, the IE effect also can be enhanced. This, in both cases, is considered to be due to the increase in the hole current flowing in the mesa section that increases the forward bias across the n+/n−-junction due to a voltage drop.
Here, letting Nd be the doping concentration in the drift layer and Vn be the forward bias applied across the n+/n−-junction, the electron density n on the n−-layer side of the n+/n−-junction can be expressed by the following expression, where k is Boltzmann constant and T is an absolute temperature:n=Nd*exp(Vn/kT).
As is apparent from the above expression, depending on the forward bias applied to the n+/n−-junction, the electron density on the cathode side is exponentially increased. To increase the amount of the forward bias, a voltage drop caused by a large current can be used. Moreover, as are described in JP-A-2003-347549, JP-T-2002-532885 and JP-A-8-316479, the amount of the forward bias can be increased by also increasing the n-type impurity concentration in the n+-layer. However, the HiGT structure described in JP-A-2003-347549, being a planar structure, causes a large reduction in the forward breakdown voltage when the n-type impurity concentration in the n+ buffer layer on the surface side is excessively high.
In the CSTBT structure described in JP-A-8-316479, the n+-buffer layer on the surface side is held between the trench gate oxide films with its electric potential continuing to the electric potential of the polysilicon through the gate oxide film. This depletes the n+-buffer layer on the surface side not only from the p-n junction but also from the boundaries of the trench gate oxide films on both sides. Thus, the n+-buffer layer on the surface side is completely depleted with a low forward bias. Therefore, although the n+-buffer layer on the surface side has a high impurity concentration, the electric field strength inside the layer is reduced. Even though the forward bias is further increased, the reduced electric field strength in the mesa section between the trenches hardly makes a local peak in the electric field.
This holds true to the principle of the MOSFET with a superjunction structure that includes in a drift section, instead of including a drift layer formed with a uniform layer of a single conductivity type, a parallel p-n structure in which vertical-layer-like n-type regions, each with an increased impurity concentration, and vertical-layer-like p-type regions are alternately joined. Thus, the CSTBT structure has such characteristics that enhance the IE effect and yet make it hard to lower the forward breakdown voltage. The n+-buffer layer on the surface side causes, between the n−-drift layer, a diffusion potential that becomes a potential barrier for holes. Thus, the hole concentration in the drift layer is increased (the first explanation).
As another explanation (the second explanation) for the reason, it can be said that the n+-buffer layer on the surface side and the n-drift layer being forward-biased causes electrons to be injected from the n+-buffer layer. Namely, in the n+/n−-junction, the n+-layer with a high impurity concentration increases the electron injection efficiency, which increases the fraction of an electron current injected into the n−-layer to hole current flowing in the n+-layer. For allowing holes to flow in the n+-layer by diffusion as minority carriers, the n+/n− junction must be forward-biased. Since the higher the impurity concentration in the n+-layer is, the smaller the concentration of holes as minority carriers in a thermal equilibrium state becomes, a higher amount of a forward bias becomes necessary for still allowing the same amount of hole current to flow with the impurity concentration in the n+-layer made higher. Since a higher forward voltage increases an electron current flowing into the n−-layer, an electron concentration is increased. The second explanation expresses the previous first explanation physically in different words. As explained above, it is known that, even in a related IGBT, such an element structure that deviates the carrier distribution to the cathode side due to the IE effect, is preferably provided for optimizing the on-voltage to turn-off loss tradeoff.
However, the above-explained optimization of the on-voltage to turn-off loss tradeoff cannot always be said to be sufficient. It is considered that the carrier density on the cathode side in the on-state must be further increased. Namely, it is not considered yet that the IE effect is sufficiently exhibited in such a MOS gate semiconductor device as a related IGBT, for example. For example, even in a device to which a trench gate structure is adopted as in the above-explained CSTBT structure or IEGT structure, although the tradeoff characteristic is improved better than that in a previous device, there are still possibilities for improvement by further miniaturization.
The manufacturing process of a semiconductor device with the trench gate structure, however, (although the manufactured trench gate structure exhibits a certain effect of improving the tradeoff as explained above) is longer and more complicated as compared with the manufacturing process of a semiconductor device with the planar structure. Thus, the rate of acceptable products of a semiconductor device with the trench gate structure is lower than the rate of acceptable products of a semiconductor device with the planar structure, which is liable to increase the product cost of the semiconductor device with the trench gate structure relatively higher than that of the semiconductor device with the planer structure.
In addition, further miniaturization of the semiconductor device with the trench gate structure regardless of the enhancing characteristics of the semiconductor device will result in a higher manufacturing cost. In the semiconductor device with the trench gate structure, an electric field concentration is liable to occur particularly at the bottom of the trench, to easily cause a breakdown in dielectric strength or avalanche breakdown, which is liable to degrade the on-voltage to breakdown voltage tradeoff. Moreover, the structure has a problem in that, when the electric potential of the gate is made negative to that of the cathode, the electric field strength at the bottom of the trench increases to further degrade the breakdown voltage.
Accordingly, there remains a need to solve the above problems and provide a semiconductor device and a method of manufacturing the device with further improved performance, namely providing a semiconductor device capable of further improving the tradeoff between the on-voltage and the turn-off loss. The present invention addresses this need.